linux-kernel - Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior

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Message-ID: <56E81103.8010903@nvidia.com>
Date:	Tue, 15 Mar 2016 19:11:23 +0530
From:	Laxman Dewangan <ldewangan@...dia.com>
To:	Mark Brown <broonie@...nel.org>
CC:	Bjorn Andersson <bjorn.andersson@...aro.org>, <robh+dt@...nel.org>,
	<pawel.moll@....com>, <mark.rutland@....com>,
	<ijc+devicetree@...lion.org.uk>, <lgirdwood@...il.com>,
	<bjorn.andersson@...ymobile.com>, <swarren@...dotorg.org>,
	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	Gandhar Dighe <gdighe@...dia.com>,
	Stuart Yates <syates@...dia.com>
Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based
 on platform behavior

On Wednesday 02 March 2016 10:05 AM, Mark Brown wrote:
> * PGP Signed by an unknown key
>
> On Wed, Mar 02, 2016 at 09:05:26AM +0530, Laxman Dewangan wrote:
>> On Wednesday 02 March 2016 09:08 AM, Mark Brown wrote:
>>> You're not trying to scale the value here, you're trying to replace the
>>> value because the PMIC is incapable of delivering the advertised ramp
>>> rate.  Trying to express this as a multiple of the advertised ramp rate
>>> is just adding complexity.
>> So should we provide absolute ramp value here for platform specific?
> Yes, otherwise if the PMIC vendor respecifies their ramp rates to
> reflect reality and the driver is updated then your DT will be broken.
>
>> Or any other suggestion to handle this situation as this is very common and
>> almost all our boards have this slowness on ramp.
> Perhaps time to have a chat with your PMIC vendors...
>

I had discussion with our HW team to get more information about this 
variation.
They said that Maxim advertise the ramp time with given condition in 
interface i.e. capacitance etc which is very generic.
We did the experiment with Maxim recommendation about the rail and its 
capacitance (2.2uF) and found that measured value is same as what they 
advertise in datasheet.

When chip team use this PMIC with Tegra hardware specs and did the 
circuit simulation to ensures how our boards should be designed for 
signal integrity they suggested that the rail capacitance should be more 
than what Maxim recommending in general to work with our silicon. So 
here condition get changed and hence the effective ramp time.

So here we will need two parameters:
advertised-ramp-delay for PMIC configurations and
ramp-delay which is measured one.

Most of time, advertised-ramp-delay is same as ramp-delay and hence one 
value from DT will be sufficient.
If there is difference then both value can be provided and 
advertised-ramp-delay  will be used for PMIC configuration and rest of 
calculation about delay will be from ramp-delay.