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Message-ID: <20160316143534.GI18387@arm.com>
Date: Wed, 16 Mar 2016 14:35:35 +0000
From: Will Deacon <will.deacon@....com>
To: Mark Rutland <mark.rutland@....com>
Cc: Timur Tabi <timur@...eaurora.org>,
Ganesh Mahendran <opensource.ganesh@...il.com>,
catalin.marinas@....com, linux-kernel@...r.kernel.org,
stable@...r.kernel.org, rrichter@...ium.com,
tchalamarla@...ium.com,
Shanker Donthineni <shankerd@...eaurora.org>,
apinski@...ium.com, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] Revert "arm64: Increase the max granular size"
On Wed, Mar 16, 2016 at 02:03:35PM +0000, Mark Rutland wrote:
> If I understand correctly, the main reason that we need this for correctness is
> non-coherent DMA to/from SLAB caches.
>
> A more general approach (and more invasive, but perhaps less so than making
> ARCH_DMA_MINALIGN usage completely dynamic) would be to determine at runtime
> whether the CWG is larger than the configured ARCH_DMA_MINALIGN, and if so,
> force the use of bounce buffers (which could be padded to the architectural
> maximum of 2K) for non-coherent DMA. That nicely degrades to not mattering for
> the case of coherent DMA.
>
> I would consider NoSnoop a separate case. It's closer to "negatively coherent",
> and always required page-aligned buffer anyway due to MMU behaviour.
What makes you say that? There are no such alignment requirements for
buffers that may be accessed with a NoSnoop transaction. On ARM, we'll
have a mismatched alias, but we'd need to solve that with explicit
cache maintenance (and my understanding is that's what things like GPU
drivers already do on x86).
Will
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