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Message-ID: <alpine.DEB.2.11.1603181031280.3978@nanos>
Date: Fri, 18 Mar 2016 10:32:48 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: Fu Wei <fu.wei@...aro.org>
cc: rjw@...ysocki.net, lenb@...nel.org, daniel.lezcano@...aro.org,
marc.zyngier@....com, hanjun.guo@...aro.org,
linux-arm-kernel@...ts.infradead.org, linaro-acpi@...ts.linaro.org,
linux-kernel@...r.kernel.org, linux-acpi@...r.kernel.org,
rruigrok@...eaurora.org, harba@...eaurora.org, cov@...eaurora.org,
timur@...eaurora.org, graeme.gregory@...aro.org,
al.stone@...aro.org, jcm@...hat.com, wei@...hat.com, arnd@...db.de,
wim@...ana.be, catalin.marinas@....com, will.deacon@....com,
Suravee.Suthikulpanit@....com, leo.duran@....com
Subject: Re: [RESEND PATCH v4 5/5] clocksource: add memory-mapped timer
support in arm_arch_timer.c
On Fri, 18 Mar 2016, fu.wei@...aro.org wrote:
> +static u32 __init arch_timer_mem_cnttidr(struct acpi_gtdt_timer_block *gt_block)
> +{
> + phys_addr_t cntctlbase_phy;
> + void __iomem *cntctlbase;
> + u32 cnttidr;
> +
> + cntctlbase_phy = (phys_addr_t)gtdt_gt_cntctlbase(gt_block);
> + if (!cntctlbase_phy) {
> + pr_err("Can't find CNTCTLBase.\n");
> + return 0;
> + }
> +
> + /*
> + * According to ARMv8 Architecture Reference Manual(ARM),
> + * the size of CNTCTLBase frame of memory-mapped timer
> + * is SZ_4K(Offset 0x000 – 0xFFF).
> + */
> + cntctlbase = ioremap(cntctlbase_phy, SZ_4K);
> + if (!cntctlbase) {
> + pr_err("Can't map CNTCTLBase\n");
> + return 0;
> + }
Why are you continuing when you can't find a base address or the remap fails?
> + /*
> + * Get Generic Timer Counter-timer Timer ID Register
> + * for Virtual Timer Capability info
> + */
> + cnttidr = arch_timer_mem_cnttidr(gt_block);
Thanks,
tglx
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