linux-kernel - [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

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Message-ID: <1458576106-24505-10-git-send-email-tthayer@opensource.altera.com>
Date:	Mon, 21 Mar 2016 11:01:46 -0500
From:	<tthayer@...nsource.altera.com>
To:	<bp@...en8.de>, <dougthompson@...ssion.com>,
	<m.chehab@...sung.com>, <robh+dt@...nel.org>, <pawel.moll@....com>,
	<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
	<galak@...eaurora.org>, <linux@....linux.org.uk>,
	<dinguyen@...nsource.altera.com>, <grant.likely@...aro.org>
CC:	<devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
	<linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <tthayer.linux@...il.com>,
	<tthayer@...nsource.altera.com>
Subject: [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry

From: Thor Thayer <tthayer@...nsource.altera.com>

Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@...nsource.altera.com>
---
v2 Match register value (l2-ecc@...06010)
v3 Set ecc_manager to beginning of system_manager. Add sysman
   phandle. Move IRQs into ecc_manager from children.
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index cce9e50..345ea97 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -599,6 +599,21 @@
 			reg = <0xffe00000 0x40000>;
 		};
 
+		eccmgr: eccmgr@...06000 {
+			compatible = "altr,socfpga-a10-ecc-manager";
+			altr,sysmgr-syscon = <&sysmgr>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 0 IRQ_TYPE_LEVEL_HIGH>;
+			ranges;
+
+			l2-ecc@...06010 {
+				compatible = "altr,socfpga-a10-l2-ecc";
+				reg = <0xffd06010 0x4>;
+			};
+		};
+
 		rst: rstmgr@...05000 {
 			#reset-cells = <1>;
 			compatible = "altr,rst-mgr";
-- 
1.7.9.5