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Message-ID: <CACRpkdYHqXWZeo=+zY2orRjHniyzcR_Z=o2ZMXtevEdxmHjWJA@mail.gmail.com>
Date:	Tue, 22 Mar 2016 12:01:58 +0100
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Thierry Reding <thierry.reding@...il.com>
Cc:	Kishon Vijay Abraham I <kishon@...com>,
	Stephen Warren <swarren@...dotorg.org>,
	Alexandre Courbot <gnurou@...il.com>,
	Andrew Bresticker <abrestic@...omium.org>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>
Subject: Re: [PATCH v10 1/9] dt-bindings: phy: Add NVIDIA Tegra XUSB pad
 controller binding

On Fri, Mar 4, 2016 at 5:19 PM, Thierry Reding <thierry.reding@...il.com> wrote:

> From: Thierry Reding <treding@...dia.com>
>
> The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
> set of lanes that are used for PCIe, SATA and USB.
>
> Signed-off-by: Thierry Reding <treding@...dia.com>
> ---
> Changes in v10:
> - clarify that the hardware documentation means something different when
>   referring to a "port" (intra-SoC connectivity)

Thierry I'm a bit out of sync, so can you resend these patches with
collected ACKs after -rc1?

Please send me the patches I can just merge into the pinctrl tree
separately if possible, I encourage any DTS changes to go in
orthogonally through ARM SoC. The DTS business I regard as
kind of its own tree.

Yours,
Linus Walleij

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