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Message-Id: <1458670171-16782-2-git-send-email-andi@firstfloor.org> Date: Tue, 22 Mar 2016 11:09:31 -0700 From: Andi Kleen <andi@...stfloor.org> To: acme@...nel.org Cc: jolsa@...nel.org, peterz@...radead.org, linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com> Subject: [PATCH 2/2] perf, tools: Fix documentation of :ppp in perf list From: Andi Kleen <ak@...ux.intel.com> Correctly document what is implemented for :ppp on Intel CPUs in recent kernels. Acked-by: Jiri Olsa <jolsa@...nel.org> Signed-off-by: Andi Kleen <ak@...ux.intel.com> --- tools/perf/Documentation/perf-list.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index 0059905..cc87111 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -40,10 +40,12 @@ address should be. The 'p' modifier can be specified multiple times: 0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid - 3 - SAMPLE_IP must have 0 skid + 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid + sample shadowing effects. For Intel systems precise event sampling is implemented with PEBS -which supports up to precise-level 2. +which supports up to precise-level 2, and precise level 3 for +some special cases On AMD systems it is implemented using IBS (up to precise-level 2). The precise modifier works with event types 0x76 (cpu-cycles, CPU -- 2.5.5
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