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Date: Wed, 23 Mar 2016 11:08:04 +0000 From: Marc Zyngier <marc.zyngier@....com> To: Alexander Stein <alexander.stein@...tec-electronic.com>, linux-kernel@...r.kernel.org Cc: Minghuan Lian <Minghuan.Lian@....com>, linux-arm-kernel@...ts.infradead.org, Thomas Gleixner <tglx@...utronix.de>, Jason Cooper <jason@...edaemon.net>, Roy Zang <roy.zang@....com>, Mingkai Hu <mingkai.hu@....com>, Stuart Yoder <stuart.yoder@....com>, Yang-Leo Li <leoyang.li@....com> Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support On 23/03/16 09:18, Alexander Stein wrote: > On Monday 07 March 2016 11:36:22, Minghuan Lian wrote: >> Some kind of NXP Layerscape SoC provides a MSI >> implementation which uses two SCFG registers MSIIR and >> MSIR to support 32 MSI interrupts for each PCIe controller. >> The patch is to support it. >> >> Signed-off-by: Minghuan Lian <Minghuan.Lian@....com> > > Tested-by: Alexander Stein <alexander.stein@...tec-electronic.com> > > Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though: >> grep eth3 /proc/interrupts >> >> 63: 49 0 MSI 134742016 Edge eth3-rx-0 >> 64: 3 0 MSI 134742017 Edge eth3-tx-0 >> 65: 4 0 MSI 134742018 Edge eth3 This is a virtual interrupt number (despite being displayed as a hwirq), computed from the PCI requester ID and the MSI index. You shouldn't infer anything from it. Thanks, M. -- Jazz is not dead. It just smells funny...
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