linux-kernel - [tip:perf/urgent] perf list: Fix documentation of :ppp

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Message-ID: <tip-4ca0d8193f8b6b2c74d05d9bbcbaa99fdd553503@git.kernel.org>
Date:	Thu, 24 Mar 2016 00:38:12 -0700
From:	tip-bot for Andi Kleen <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	peterz@...radead.org, linux-kernel@...r.kernel.org,
	acme@...hat.com, mingo@...nel.org, ak@...ux.intel.com,
	tglx@...utronix.de, hpa@...or.com, jolsa@...nel.org
Subject: [tip:perf/urgent] perf list: Fix documentation of :ppp

Commit-ID:  4ca0d8193f8b6b2c74d05d9bbcbaa99fdd553503
Gitweb:     http://git.kernel.org/tip/4ca0d8193f8b6b2c74d05d9bbcbaa99fdd553503
Author:     Andi Kleen <ak@...ux.intel.com>
AuthorDate: Mon, 21 Mar 2016 08:56:33 -0700
Committer:  Arnaldo Carvalho de Melo <acme@...hat.com>
CommitDate: Tue, 22 Mar 2016 10:01:45 -0300

perf list: Fix documentation of :ppp

Correctly document what is implemented for :ppp on Intel CPUs in recent
kernels.

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Acked-by: Jiri Olsa <jolsa@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Link: http://lkml.kernel.org/r/1458575793-12091-2-git-send-email-andi@firstfloor.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 tools/perf/Documentation/perf-list.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt
index 79483f4..ec723d0 100644
--- a/tools/perf/Documentation/perf-list.txt
+++ b/tools/perf/Documentation/perf-list.txt
@@ -40,10 +40,12 @@ address should be. The 'p' modifier can be specified multiple times:
  0 - SAMPLE_IP can have arbitrary skid
  1 - SAMPLE_IP must have constant skid
  2 - SAMPLE_IP requested to have 0 skid
- 3 - SAMPLE_IP must have 0 skid
+ 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
+     sample shadowing effects.
 
 For Intel systems precise event sampling is implemented with PEBS
-which supports up to precise-level 2.
+which supports up to precise-level 2, and precise level 3 for
+some special cases
 
 On AMD systems it is implemented using IBS (up to precise-level 2).
 The precise modifier works with event types 0x76 (cpu-cycles, CPU