linux-kernel - [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed

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Message-Id: <1458974276-10325-2-git-send-email-zhengxing@rock-chips.com>
Date:	Sat, 26 Mar 2016 14:37:53 +0800
From:	Xing Zheng <zhengxing@...k-chips.com>
To:	linux-rockchip@...ts.infradead.org
Cc:	heiko@...ech.de, huangtao@...k-chips.com, jay.xu@...k-chips.com,
	elaine.zhang@...k-chips.com, dianders@...omium.org,
	Xing Zheng <zhengxing@...k-chips.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed

On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,
there is incorrect to select bit_0 and bit_1 as the main and alternate
parents for LPLL/BPLL. They should be configurable.

Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>
---

Changes in v5: None
Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-cpu.c |   15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 5556849..4bb130c 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -258,7 +258,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
 		return ERR_PTR(-ENOMEM);
 
 	init.name = name;
-	init.parent_names = &parent_names[0];
+	init.parent_names = &parent_names[reg_data->mux_core_main];
 	init.num_parents = 1;
 	init.ops = &rockchip_cpuclk_ops;
 
@@ -276,10 +276,10 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
 	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
 	cpuclk->hw.init = &init;
 
-	cpuclk->alt_parent = __clk_lookup(parent_names[1]);
+	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
 	if (!cpuclk->alt_parent) {
-		pr_err("%s: could not lookup alternate parent\n",
-		       __func__);
+		pr_err("%s: could not lookup alternate parent: (%d)\n",
+		       __func__, reg_data->mux_core_alt);
 		ret = -EINVAL;
 		goto free_cpuclk;
 	}
@@ -291,10 +291,11 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
 		goto free_cpuclk;
 	}
 
-	clk = __clk_lookup(parent_names[0]);
+	clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
 	if (!clk) {
-		pr_err("%s: could not lookup parent clock %s\n",
-		       __func__, parent_names[0]);
+		pr_err("%s: could not lookup parent clock: (%d) %s\n",
+		       __func__, reg_data->mux_core_main,
+		       parent_names[reg_data->mux_core_main]);
 		ret = -EINVAL;
 		goto free_alt_parent;
 	}
-- 
1.7.9.5