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Message-ID: <1608479.lxyeMomFsd@diego>
Date:	Sun, 27 Mar 2016 23:26:52 +0200
From:	Heiko Stübner <heiko@...ech.de>
To:	Xing Zheng <zhengxing@...k-chips.com>
Cc:	linux-rockchip@...ts.infradead.org, huangtao@...k-chips.com,
	jay.xu@...k-chips.com, elaine.zhang@...k-chips.com,
	dianders@...omium.org, Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed

Am Samstag, 26. März 2016, 14:37:53 schrieb Xing Zheng:
> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,
> there is incorrect to select bit_0 and bit_1 as the main and alternate
> parents for LPLL/BPLL. They should be configurable.
> 
> Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>

I've folded this fix into the original patch [0]


Thanks
Heiko


[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=268aebaa2410152bf91ea1ede6b284ff8138822d

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