linux-kernel - Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Mon, 28 Mar 2016 15:40:58 -0500
From:	Matthew McClintock <mmcclint@...eaurora.org>
To:	Guenter Roeck <linux@...ck-us.net>
Cc:	andy.gross@...aro.org, linux-arm-msm@...r.kernel.org,
	"qca-upstream.external" <qca-upstream.external@....qualcomm.com>,
	Wim Van Sebroeck <wim@...ana.be>,
	"open list:WATCHDOG DEVICE DRIVERS" <linux-watchdog@...r.kernel.org>,
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 07/17] watchdog: qcom: add option for standalone watchdog not in timer block

On Mar 28, 2016, at 1:13 PM, Guenter Roeck <linux@...ck-us.net> wrote:
> 
>>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg
>>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is
>>> undefined.
>> 
>> I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts.
>> 
> That is from the APQ8064 datasheet. 

So taken from the timer offset 0x0208A000 I just have a generic counter register CPU0_APCS_GPT0_CNT at 0x8

What doc are you looking at?

-M