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Message-ID: <1459351668-14622-8-git-send-email-tthayer@opensource.altera.com>
Date: Wed, 30 Mar 2016 10:27:48 -0500
From: <tthayer@...nsource.altera.com>
To: <bp@...en8.de>, <dougthompson@...ssion.com>,
<m.chehab@...sung.com>, <robh+dt@...nel.org>, <pawel.moll@....com>,
<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
<galak@...eaurora.org>, <linux@....linux.org.uk>,
<dinguyen@...nsource.altera.com>, <grant.likely@...aro.org>
CC: <devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
<linux-edac@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<tthayer@...nsource.altera.com>
Subject: [PATCH 7/7] ARM: dts: Add Altera Arria10 OCRAM EDAC devicetree entry
From: Thor Thayer <tthayer@...nsource.altera.com>
Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@...nsource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 519e9e4..27cc497 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -612,6 +612,11 @@
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
};
+
+ ocram-ecc@...c3000 {
+ compatible = "altr,socfpga-a10-ocram-ecc";
+ reg = <0xff8c3000 0x400>;
+ };
};
rst: rstmgr@...05000 {
--
1.7.9.5
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