lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <56FC1E92.60403@synopsys.com>
Date:	Wed, 30 Mar 2016 11:44:34 -0700
From:	John Youn <John.Youn@...opsys.com>
To:	Felipe Balbi <balbi@...nel.org>,
	John Youn <John.Youn@...opsys.com>,
	"Roger Quadros" <rogerq@...com>
CC:	"nsekhar@...com" <nsekhar@...com>,
	"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] usb: dwc3: core: Introduce dwc3_device_reinit()

On 3/23/2016 11:52 PM, Felipe Balbi wrote:
> 
> Hi,
> 
> John Youn <John.Youn@...opsys.com> writes:
>> [ text/plain ]
>> On 3/21/2016 11:40 PM, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>> John Youn <John.Youn@...opsys.com> writes:
>>>> [ text/plain ]
>>>> On 3/18/2016 12:17 PM, John Youn wrote:
>>>>> On 3/16/2016 6:56 AM, Felipe Balbi wrote:
>>>>>>
>>>>>> heh, +john
>>>>>>
>>>>>> Felipe Balbi <balbi@...nel.org> writes:
>>>>>>> [ text/plain ]
>>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> Roger Quadros <rogerq@...com> writes:
>>>>>>>> [ text/plain ]
>>>>>>>> We will need this function for a workaround.
>>>>>>>> The function issues a softreset only to the device
>>>>>>>> controller and performs minimal re-initialization
>>>>>>>> so that the device controller can be usable.
>>>>>>>>
>>>>>>>> As some code is similar to dwc3_core_init() take out
>>>>>>>> common code into dwc3_get_gctl_quirks().
>>>>>>>>
>>>>>>>> We add a new member (prtcap_mode) to struct dwc3 to
>>>>>>>> keep track of the current mode in the PRTCAPDIR register.
>>>>>>>>
>>>>>>>> Signed-off-by: Roger Quadros <rogerq@...com>
>>>>>>>
>>>>>>> I must say, I don't like this at all :-p There's ONE known silicon which
>>>>>>> needs this because of a poor silicon integration which took an IP with a
>>>>>>> known erratum where it can't be made to work on lower speeds and STILL
>>>>>>> was integrated without a superspeed PHY.
>>>>>>>
>>>>>>> There's a reason why I never tried to push this upstream myself ;-)
>>>>>>>
>>>>>>> I'm really thinking we might be better off adding a quirk flag to skip
>>>>>>> the metastability workaround and allow this ONE silicon to set the
>>>>>>> controller to lower speed.
>>>>>>>
>>>>>>> John, can you check with your colleagues if we would ever fall into
>>>>>>> STAR#9000525659 if we set maximum speed to high speed during driver
>>>>>>> probe and never touch it again ? I would assume we don't really fall
>>>>>>> into the metastability workaround, right ? We're not doing any sort of
>>>>>>> PM for dwc3...
>>>>>>>
>>>>
>>>> Hi Felipe,
>>>>
>>>> Do you mean to keep DCFG.speed to SS and set dwc->maximum_speed to HS?
>>>> I don't see an issue with that as long as we always ignore
>>>> dwc->maximum_speed when programming DCFG.speed for all affected
>>>> versions of the core. As long as the DCFG.speed = SS, you should not
>>>> hit the STAR.
>>>
>>> I actually mean changing DCFG.speed during driver probe and never
>>> touching it again. Would that still cause problems ?
>>>
>>
>> In that case I'm not sure. The engineer who would know is off until
>> next week so I'll get back to you as soon as I can talk to him about
>> it.
> 

So the engineers said that this issue can occur while set to HS and
the run/stop bit is changed so it seems that won't work.

Regards,
John

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ