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Date: Thu, 31 Mar 2016 13:16:09 -0700
From: Kamal Mostafa <kamal@...onical.com>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org,
kernel-team@...ts.ubuntu.com
Cc: Stephen Boyd <sboyd@...eaurora.org>,
Kamal Mostafa <kamal@...onical.com>
Subject: [PATCH 4.2.y-ckt 156/218] clk: qcom: msm8960: Fix ce3_src register offset
4.2.8-ckt7 -stable review patch. If anyone has any objections, please let me know.
---8<------------------------------------------------------------
From: Stephen Boyd <sboyd@...eaurora.org>
commit 0f75e1a370fd843c9e508fc1ccf0662833034827 upstream.
The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@...aro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@...eaurora.org>
Signed-off-by: Kamal Mostafa <kamal@...onical.com>
---
drivers/clk/qcom/gcc-msm8960.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index eb6a4f9..8470ea4 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2753,7 +2753,7 @@ static struct clk_rcg ce3_src = {
},
.freq_tbl = clk_tbl_ce3,
.clkr = {
- .enable_reg = 0x2c08,
+ .enable_reg = 0x36c0,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "ce3_src",
--
2.7.4
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