linux-kernel - Re: [PATCH 04/18] ARM: dts: vf610: add on-chip SRAM

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20160331083325.GX28207@tiger>
Date:	Thu, 31 Mar 2016 16:33:25 +0800
From:	Shawn Guo <shawnguo@...nel.org>
To:	Stefan Agner <stefan@...er.ch>
Cc:	mturquette@...libre.com, sboyd@...eaurora.org,
	kernel@...gutronix.de, sergeimir@...raft.com, tglx@...utronix.de,
	jason@...edaemon.net, marc.zyngier@....com, robh+dt@...nel.org,
	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH 04/18] ARM: dts: vf610: add on-chip SRAM

On Wed, Mar 09, 2016 at 06:16:45PM -0800, Stefan Agner wrote:
> Add Vybrids massive on-chip SRAM areas. Make use of the memory
> region functionality to denominate the retained SRAM area in
> LPSTOP2 and LPSTOP3.
> 
> Signed-off-by: Stefan Agner <stefan@...er.ch>

This one looks fine to me.  I was going to pick it up separately, but it
doesn't apply.

Shawn

> ---
>  arch/arm/boot/dts/vfxxx.dtsi | 37 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
> index 909988d..b038ea4 100644
> --- a/arch/arm/boot/dts/vfxxx.dtsi
> +++ b/arch/arm/boot/dts/vfxxx.dtsi
> @@ -91,6 +91,43 @@
>  		interrupt-parent = <&gpc>;
>  		ranges;
>  
> +		ocram0: sram@...00000 {
> +			compatible = "mmio-sram";
> +			reg = <0x3f000000 0x40000>;
> +
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0x3f000000 0x40000>;
> +
> +			stbyram1@0 {
> +				reg = <0x0 0x4000>;
> +				label = "stbyram1";
> +				pool;
> +			};
> +
> +			stbyram2@...0 {
> +				reg = <0x4000 0xc000>;
> +				label = "stbyram2";
> +				pool;
> +			};
> +		};
> +
> +		ocram1: sram@...40000 {
> +			compatible = "mmio-sram";
> +			reg = <0x3f040000 0x40000>;
> +		};
> +
> +		gfxram0: sram@...00000 {
> +			compatible = "mmio-sram";
> +			reg = <0x3f400000 0x80000>;
> +		};
> +
> +		/* used by L2 cache */
> +		gfxram1: sram@...80000 {
> +			compatible = "mmio-sram";
> +			reg = <0x3f480000 0x80000>;
> +		};
> +
>  		aips0: aips-bus@...00000 {
>  			compatible = "fsl,aips-bus", "simple-bus";
>  			#address-cells = <1>;
> -- 
> 2.7.2
> 
>