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Message-ID: <20160331183130.GR2350@sirena.org.uk>
Date: Thu, 31 Mar 2016 11:31:30 -0700
From: Mark Brown <broonie@...nel.org>
To: Laxman Dewangan <ldewangan@...dia.com>
Cc: Bjorn Andersson <bjorn@...o.se>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Liam Girdwood <lgirdwood@...il.com>,
Stephen Warren <swarren@...dotorg.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Gandhar Dighe <gdighe@...dia.com>,
Stuart Yates <syates@...dia.com>
Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based
on platform behavior
On Thu, Mar 31, 2016 at 11:17:38PM +0530, Laxman Dewangan wrote:
> HW and chip team did simulation with tegra and PMIC and found that the board
> needs more capacitance then what Vendor recommended for proper signal
> conditioning on interface. So they put the difference capactitance value and
> this causes deviation in ramp delay from advertised value. In out design, we
> measured the ramp time as 50mv/us when PMIC is configured for 100mV/us.
> So for all settling time, we need to use the ramp as 50mV/us.
> From DT, I will provide regulator-ramp-delay as 50mv/us.
> But I do not have property for saying 100mv/us for PMIC configurations and
> this is what makes need of 2nd property.
So the PMIC actually has a setting for the rate you're seeing but for
some resaon you can't use it?
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