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Message-Id: <4a62ba36cf4fb77ea35dee1f5992e0e7c48dad14.1459397558.git.len.brown@intel.com>
Date: Thu, 31 Mar 2016 00:13:51 -0400
From: Len Brown <lenb@...nel.org>
To: x86@...nel.org
Cc: linux-kernel@...r.kernel.org, Len Brown <len.brown@...el.com>
Subject: [PATCH 5/9] x86 tsc_msr: Add Airmont reference clock values
From: Len Brown <len.brown@...el.com>
per the Intel 64 and IA-32 Architecture Software Developer's Manual...
Add the reference clock for Intel Atom Processors
Based on the Airmont Microarchitecture.
Reported-by: Stephane Gasparini <stephane.gasparini@...el.com>
Signed-off-by: Len Brown <len.brown@...el.com>
---
arch/x86/kernel/tsc_msr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 19f2a9a..59c371e 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -13,7 +13,7 @@
#include <asm/apic.h>
#include <asm/param.h>
-#define MAX_NUM_FREQS 8
+#define MAX_NUM_FREQS 9
/*
* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@@ -40,6 +40,9 @@ static struct freq_desc freq_desc_tables[] = {
{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
/* ANN - Intel Atom processor Z3500 series */
{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
+ /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
+ { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
+ 80000, 93300, 90000, 88900, 87500 } },
};
static int match_cpu(u8 family, u8 model)
--
2.8.0.rc4.16.g56331f8
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