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Message-Id: <1459455431-12687-175-git-send-email-kamal@canonical.com>
Date: Thu, 31 Mar 2016 13:16:27 -0700
From: Kamal Mostafa <kamal@...onical.com>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org,
kernel-team@...ts.ubuntu.com
Cc: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Kamal Mostafa <kamal@...onical.com>
Subject: [PATCH 4.2.y-ckt 174/218] clk: qcom: msm8960: fix ce3_core clk enable register
4.2.8-ckt7 -stable review patch. If anyone has any objections, please let me know.
---8<------------------------------------------------------------
From: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
commit 732d6913691848db9fabaa6a25b4d6fad10ddccf upstream.
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@...eaurora.org>
Signed-off-by: Kamal Mostafa <kamal@...onical.com>
---
drivers/clk/qcom/gcc-msm8960.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 8470ea4..476d209 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 5,
.clkr = {
- .enable_reg = 0x36c4,
+ .enable_reg = 0x36cc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce3_core_clk",
--
2.7.4
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