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Message-ID: <1459501969-7083-1-git-send-email-jszhang@marvell.com>
Date: Fri, 1 Apr 2016 17:12:49 +0800
From: Jisheng Zhang <jszhang@...vell.com>
To: <davem@...emloft.net>, <mw@...ihalf.com>,
<thomas.petazzoni@...e-electrons.com>
CC: <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
Jisheng Zhang <jszhang@...vell.com>
Subject: [PATCH] net: mvneta: use cache_line_size() to get cacheline size
L1_CACHE_BYTES may not be the real cacheline size, use cache_line_size
to determine the cacheline size in runtime.
Signed-off-by: Jisheng Zhang <jszhang@...vell.com>
Suggested-by: Marcin Wojtas <mw@...ihalf.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 5880871..b1db000 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -299,7 +299,7 @@
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN, \
- L1_CACHE_BYTES)
+ cache_line_size())
#define IS_TSO_HEADER(txq, addr) \
((addr >= txq->tso_hdrs_phys) && \
--
2.8.0.rc3
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