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Date:	Fri, 1 Apr 2016 11:30:48 +0200
From:	Stephane Gasparini <stephane.gasparini@...ux.intel.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	Len Brown <lenb@...nel.org>, x86@...nel.org,
	linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
	Len Brown <len.brown@...el.com>
Subject: Re: [PATCH] x86: Calculate MHz using APERF/MPERF for cpuinfo and scaling_cur_freq

my comment was about your comment that MSR have wrapped however many times



> On Apr 1, 2016, at 10:03 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> 
> That is; if userspace doesn't request a freq reading we can go without
> reading this for a very long time.
> 
>> +
>> +	rdmsrl(MSR_IA32_APERF, aperf);
>> +	rdmsrl(MSR_IA32_MPERF, mperf);
>> +
>> +	aperf_delta = aperf - s->aperf;
>> +	mperf_delta = mperf - s->mperf;
> 
> That means these delta's can be arbitrarily large, in fact the MSRs can
> have wrapped however many times.

The MSRs will not wrap that often.

—
Steph




> On Apr 1, 2016, at 10:29 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> 
> On Fri, Apr 01, 2016 at 10:23:23AM +0200, Peter Zijlstra wrote:
>> 
>> Trim your emails
>> 
>> On Fri, Apr 01, 2016 at 10:16:42AM +0200, Stephane Gasparini wrote:
>> 
>>>> That means these delta's can be arbitrarily large, in fact the MSRs can
>>>> have wrapped however many times.
>>> 
>>> 64 bits is 18 446 744 073 709 551 615
>>> 
>>> so even assuming a 10 GHz frequency if my math are good this is more than
>>> 58 years before the MSR wrap around, assuming the device ran always at max
>>> freq.
>> 
>> fair enough.. but going with 10Ghz, cpu_khz would be 10e6 ~ 33 bits,
> 
> I can't do maths this morning; 23 bits
> 
>> which effectively reduces the wrap/overflow time to just 31 bits, which
>> per that frequency is just ~1/4th of a second.
> 
> 41 giving lots more, but a reasonable time to wrap/overflow.
> --
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