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Message-ID: <CACRpkdYDPyQiEpxLcZSK35zdDe3MwyxBADwMBcoRnZoz3jbstQ@mail.gmail.com>
Date: Mon, 4 Apr 2016 15:57:50 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Cristina Ciocan <cristina.ciocan@...el.com>
Cc: Mathias Nyman <mathias.nyman@...ux.intel.com>,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Irina Tirdea <irina.tirdea@...el.com>,
Octavian Purdila <octavian.purdila@...el.com>
Subject: Re: [PATCH v4 1/6] pinctrl: baytrail: Add pin control data structures
On Fri, Apr 1, 2016 at 1:00 PM, Cristina Ciocan
<cristina.ciocan@...el.com> wrote:
> In order to implement pin control for Baytrail, we need data structures
> in which to store and pass along pin, group, function, community and SOC
> data information.
>
> Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS controller data:
> - pins (for all controllers),
> - pad map for pins (for all controllers; we need this since pads
> are not ordered),
> - groups (for SCORE and SUS controllers),
> - functions (for SCORE and SUS controllers),
> - communities (for all controllers),
> - soc specific data gathering all of the above and the ACPI UID
> (for all controllers)
> This information is useful for pin control functionality. NCORE data is
> lighter than the other two controllers' due to lack of pin documentation in
> the public datasheet.
>
> Datasheet:
> http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html
>
> Signed-off-by: Cristina Ciocan <cristina.ciocan@...el.com>
Patch applied with Mika's ACK.
Yours,
Linus Walleij
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