linux-kernel - Re: [PATCH v2 5/5] dmaengine: qcom: bam_dma: rename BAM_MAX_DATA

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Message-ID: <57052B83.4000208@linaro.org>
Date:	Wed, 6 Apr 2016 18:30:11 +0300
From:	Stanimir Varbanov <stanimir.varbanov@...aro.org>
To:	Vinod Koul <vinod.koul@...el.com>,
	Stanimir Varbanov <stanimir.varbanov@...aro.org>
Cc:	Rob Herring <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Andy Gross <andy.gross@...aro.org>,
	linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
	dmaengine@...r.kernel.org, Sinan Kaya <okaya@...eaurora.org>,
	Pramod Gurav <gpramod@...eaurora.org>
Subject: Re: [PATCH v2 5/5] dmaengine: qcom: bam_dma: rename BAM_MAX_DATA_SIZE
 define

On 04/06/2016 02:47 AM, Vinod Koul wrote:
> On Wed, Apr 06, 2016 at 01:56:22AM +0300, Stanimir Varbanov wrote:
>> It seems that the define has not been with acurate name and
>> makes confusion while reading the code. The more acurate
>> name should be BAM_FIFO_SIZE.
> 
> And not sure by that, what do you mean by FIFO size. In dmaengine context we

By BAM_FIFO_SIZE I meant a FIFO depth for hw descriptors, i.e. how many
hw descriptors could be pushed into the descriptor FIFO. In our case we
wrote BAM_P_FIFO_SIZES register with SZ_32K - 8, which means that the
FIFO will be 4095 hw descriptors deep.

In fact the important patch in this series 4/5 where I corrected the
value we wrote in BAM_P_FIFO_SIZES register.

4/5 and 5/5 can be postponed till we have better decision...

-- 
regards,
Stan