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Message-Id: <20160410183505.028843746@linuxfoundation.org>
Date: Sun, 10 Apr 2016 11:35:32 -0700
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, Alexey Brodkin <abrodkin@...opsys.com>,
Rob Herring <robh@...nel.org>,
Phil Reid <preid@...ctromag.com.au>,
"David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
Sergei Shtylyov <sergei.shtylyov@...entembedded.com>,
Vineet Gupta <vgupta@...opsys.com>
Subject: [PATCH 4.5 155/238] ARC: [plat-axs10x] add Ethernet PHY description in .dts
4.5-stable review patch. If anyone has any objections, please let me know.
------------------
From: Alexey Brodkin <Alexey.Brodkin@...opsys.com>
commit 667a490bdb6e27db0887d2ca515b907d6aa87118 upstream.
Commit e34d65696d2e ("stmmac: create of compatible mdio bus for stmmac
driver") broke DW GMAC functionality on ARC AXS10x boards:
That's what happens on eth0 up:
--------------------------->8------------------------
| libphy: PHY stmmac-0:ffffffff not found
| eth0: Could not attach to PHY
| stmmac_open: Cannot attach to PHY (error: -19)
--------------------------->8------------------------
Simplest solution is to add PHY description in board's .dts.
And so we do here.
Signed-off-by: Alexey Brodkin <abrodkin@...opsys.com>
Cc: Rob Herring <robh@...nel.org>
Cc: Phil Reid <preid@...ctromag.com.au>
Cc: David S. Miller <davem@...emloft.net>
Cc: linux-kernel@...r.kernel.org
Cc: netdev@...r.kernel.org
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
Signed-off-by: Vineet Gupta <vgupta@...opsys.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
arch/arc/boot/dts/axs10x_mb.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -47,6 +47,14 @@
clocks = <&apbclk>;
clock-names = "stmmaceth";
max-speed = <100>;
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
};
ehci@...0000 {
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