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Message-Id: <20160410183507.402324946@linuxfoundation.org>
Date:	Sun, 10 Apr 2016 11:36:21 -0700
From:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:	linux-kernel@...r.kernel.org
Cc:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	stable@...r.kernel.org, Zhang Qing <zhangqing@...k-chips.com>,
	Heiko Stuebner <heiko@...ech.de>
Subject: [PATCH 4.5 204/238] clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster

4.5-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Heiko Stuebner <heiko@...ech.de>

commit 535ebd428aeb07c3327947281306f2943f2c9faa upstream.

Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@...k-chips.com>
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
Reviewed-by: zhangqing <zhangqing@...k-chips.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/clk/rockchip/clk-rk3368.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -165,7 +165,7 @@ static const struct rockchip_cpuclk_reg_
 	.core_reg = RK3368_CLKSEL_CON(0),
 	.div_core_shift = 0,
 	.div_core_mask = 0x1f,
-	.mux_core_shift = 15,
+	.mux_core_shift = 7,
 };
 
 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {


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