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Message-ID: <a31a31ec563059899440ea512a34aa19@codeaurora.org>
Date: Mon, 11 Apr 2016 13:21:06 +0530
From: gpramod@...eaurora.org
To: Stanimir Varbanov <stanimir.varbanov@...aro.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Vinod Koul <vinod.koul@...el.com>,
Andy Gross <andy.gross@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
dmaengine@...r.kernel.org, Sinan Kaya <okaya@...eaurora.org>
Subject: Re: [PATCH v2 2/5] dmaengine: qcom: bam_dma: clear BAM interrupt only
if it is rised
On 2016-04-06 04:26, Stanimir Varbanov wrote:
> Currently we write BAM_IRQ_CLR register with zero even when no
> BAM_IRQ occured. This write has some bad side effects when the
> BAM instance is for the crypto engine. In case of crypto engine
> some of the BAM registers are xPU protected and they cannot be
> controlled by the driver.
>
> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@...aro.org>
> Reviewed-by: Andy Gross <andy.gross@...aro.org>
> ---
> drivers/dma/qcom/bam_dma.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
Tested-by: Pramod Gurav <gpramod@...eaurora.org>
> diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
> index a486bc0f82e0..789d5f836bf7 100644
> --- a/drivers/dma/qcom/bam_dma.c
> +++ b/drivers/dma/qcom/bam_dma.c
> @@ -801,13 +801,17 @@ static irqreturn_t bam_dma_irq(int irq, void
> *data)
> if (srcs & P_IRQ)
> tasklet_schedule(&bdev->task);
>
> - if (srcs & BAM_IRQ)
> + if (srcs & BAM_IRQ) {
> clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
>
> - /* don't allow reorder of the various accesses to the BAM registers
> */
> - mb();
> + /*
> + * don't allow reorder of the various accesses to the BAM
> + * registers
> + */
> + mb();
>
> - writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
> + writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
> + }
>
> return IRQ_HANDLED;
> }
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