linux-kernel - Re: [PATCH v6 03/10] usb: dwc3: omap: Pass VBUS and ID events transparently

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Message-ID: <570BA0B1.1060404@ti.com>
Date:	Mon, 11 Apr 2016 16:03:45 +0300
From:	Roger Quadros <rogerq@...com>
To:	Felipe Balbi <balbi@...nel.org>
CC:	<tony@...mide.com>, <Joao.Pinto@...opsys.com>,
	<sergei.shtylyov@...entembedded.com>, <peter.chen@...escale.com>,
	<jun.li@...escale.com>, <grygorii.strashko@...com>,
	<yoshihiro.shimoda.uh@...esas.com>, <nsekhar@...com>,
	<linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-omap@...r.kernel.org>
Subject: Re: [PATCH v6 03/10] usb: dwc3: omap: Pass VBUS and ID events
 transparently

On 11/04/16 15:18, Felipe Balbi wrote:
> 
> Hi,
> 
> Roger Quadros <rogerq@...com> writes:
>> Don't make any decisions regarding VBUS session based on ID
>> status. That is best left to the OTG core.
> 
> what about builds who don't want OTG and/or dual-role ?
> 
>> Pass ID and VBUS events independent of each other so that OTG
>> core knows exactly what to do.
>>
>> This makes dual-role with extcon work with OTG irq on OMAP platforms.
>>
>> Signed-off-by: Roger Quadros <rogerq@...com>
>> ---
>>  drivers/usb/dwc3/dwc3-omap.c | 15 ++++++---------
>>  1 file changed, 6 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
>> index 51ca098..c9b918d 100644
>> --- a/drivers/usb/dwc3/dwc3-omap.c
>> +++ b/drivers/usb/dwc3/dwc3-omap.c
>> @@ -233,19 +233,14 @@ static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
>>  		}
>>  
>>  		val = dwc3_omap_read_utmi_ctrl(omap);
>> -		val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG
>> -				| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
>> -				| USBOTGSS_UTMI_OTG_CTRL_SESSEND);
>> -		val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID
>> -				| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
>> +		val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
> 
> this creates the possibility of having a USB peripheral with VBUS_VALID,
> right 

Sorry, I didn't get what you meant.

> 
>>  		dwc3_omap_write_utmi_ctrl(omap, val);
>>  		break;
>>  
>>  	case OMAP_DWC3_VBUS_VALID:
>>  		val = dwc3_omap_read_utmi_ctrl(omap);
>>  		val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
>> -		val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG
>> -				| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
>> +		val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
>>  				| USBOTGSS_UTMI_OTG_CTRL_SESSVALID
>>  				| USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT;
> 
> I remember discussing this with TI's IP owner back in OMAP5 days. This
> code was a result of talking to that guy and was, back then, tested by
> Silicon Validation team. I would strongly advise that before changing
> these bits you check with whoever's currently handling this IP inside TI
> to make sure your changes are still within the expectations of the
> wrapper block.
> 
OK, I wasn't aware about this. I will check with the Silicon team.

cheers,
-roger