[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <1460343044-1474-1-git-send-email-jui.nee.tan@intel.com>
Date: Mon, 11 Apr 2016 10:50:41 +0800
From: Tan Jui Nee <jui.nee.tan@...el.com>
To: mika.westerberg@...ux.intel.com, heikki.krogerus@...ux.intel.com,
andriy.shevchenko@...ux.intel.com, tglx@...utronix.de,
mingo@...hat.com, hpa@...or.com, x86@...nel.org,
ptyser@...-inc.com, lee.jones@...aro.org
Cc: linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
jui.nee.tan@...el.com, jonathan.yong@...el.com,
ong.hock.yu@...el.com, weifeng.voon@...el.com,
wan.ahmad.zainie.wan.mohamad@...el.com
Subject: [PATCH 0/3] pinctrl/broxton: enable platform device in the absent of ACPI enumeration
Hi,
The patches are to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind with
Apollo Lake Pinctrl GPIO platform driver.
The MMIO BAR is accessed over the Primary to Sideband bridge
(P2SB). Since the BIOS prevents the P2SB device from being
enumerated by the PCI subsystem, so we need to hide/unhide P2SB
to lookup the P2SB BAR and pass the PCI BAR address to the gpio
platform driver.
All these three patches have dependencies on each other.
Andy Shevchenko (1):
x86/platform/p2sb: New Primary to Sideband bridge support driver for
Intel SOC's
Tan Jui Nee (2):
pinctrl/broxton: enable platform device in the absent of ACPI
enumeration
mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in
non-ACPI system
arch/x86/Kconfig | 4 ++
arch/x86/include/asm/p2sb.h | 27 ++++++++
arch/x86/platform/intel/Makefile | 1 +
arch/x86/platform/intel/p2sb.c | 99 ++++++++++++++++++++++++++
drivers/mfd/Kconfig | 3 +-
drivers/mfd/lpc_ich.c | 119 ++++++++++++++++++++++++++++++++
drivers/pinctrl/intel/pinctrl-broxton.c | 43 ++++++++----
7 files changed, 283 insertions(+), 13 deletions(-)
create mode 100644 arch/x86/include/asm/p2sb.h
create mode 100644 arch/x86/platform/intel/p2sb.c
--
1.9.1
Powered by blists - more mailing lists