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Message-ID: <570CF822.4050002@nvidia.com>
Date: Tue, 12 Apr 2016 18:59:06 +0530
From: Laxman Dewangan <ldewangan@...dia.com>
To: Mark Brown <broonie@...nel.org>
CC: Bjorn Andersson <bjorn@...o.se>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Liam Girdwood <lgirdwood@...il.com>,
"Stephen Warren" <swarren@...dotorg.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Gandhar Dighe <gdighe@...dia.com>,
"Stuart Yates" <syates@...dia.com>
Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based
on platform behavior
On Tuesday 12 April 2016 06:32 AM, Mark Brown wrote:
> * PGP Signed by an unknown key
>
> On Tue, Apr 05, 2016 at 01:31:41PM +0530, Laxman Dewangan wrote:
>> On Friday 01 April 2016 09:41 PM, Mark Brown wrote:
>> Now there is not really equation that how it control dV/dt with required
>> current vs regulator's current limit current limit.
> I'm having a hard time tying this in with what you're saying. You're
> saying we have a predictable limit based on some hard maximum inrush
> current but we can't tell what that limit is? What I'd expect is that
> we'd get the spec limit up to some maximum and then cap out at that.
>
>
I have put my understanding based on datasheet and observation but it
seems I am missing some important information which is making difficult
to understand further here.
We are not crossing the maximum limit of the load on the rail per
datasheet. We just changed the output capacitor in the platforms and saw
deviation.
I think I need to go again to Vendor to find out that why changing of
capacitor making the deviation in ramp delay and what is the relation.
Probably, that may help here.
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