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Message-ID: <20160412152336.GF25160@ulmo.ba.sec>
Date: Tue, 12 Apr 2016 17:23:36 +0200
From: Thierry Reding <thierry.reding@...il.com>
To: Rhyland Klein <rklein@...dia.com>
Cc: Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Stephen Warren <swarren@...dotorg.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Alexandre Courbot <gnurou@...il.com>,
linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1
On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
> Use a new Tegra210 version of the pll_register_pllre function to
> allow setting the proper settings for the m and n div fields.
>
> Additionally define PLL_RE_OUT1 on Tegra210.
It'd be nice to specify what that additional clock is used for. No need
to repost for that, I can add it when applying.
Thierry
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