linux-kernel - [PATCH v2 3/8] PM / devfreq: exynos: Add the detailed correlation for Exynos5422 bus

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Message-id: <1460701975-24178-4-git-send-email-cw00.choi@samsung.com>
Date:	Fri, 15 Apr 2016 15:32:50 +0900
From:	Chanwoo Choi <cw00.choi@...sung.com>
To:	myungjoo.ham@...sung.com, kyungmin.park@...sung.com,
	k.kozlowski@...sung.com, tomasz.figa@...il.com,
	s.nawrocki@...sung.com, kgene@...nel.org
Cc:	robh@...nel.org, rjw@...ysocki.net, robh+dt@...nel.org,
	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	linux@....linux.org.uk, linux.amoon@...il.com,
	m.reichl@...etechno.de, tjakobi@...h.uni-bielefeld.de,
	inki.dae@...sung.com, cw00.choi@...sung.com,
	linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
	linux-samsung-soc@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org
Subject: [PATCH v2 3/8] PM / devfreq: exynos: Add the detailed correlation for
 Exynos5422 bus

This patch adds the detailed corrleation between sub-blocks and power line
for Exynos5422.

Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>
---
 .../devicetree/bindings/devfreq/exynos-bus.txt        | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index 7dbd4abfca33..d3ec8e676b6b 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -104,6 +104,25 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
 		|--- LCD0
 		|--- ISP
 
+- In case of Exynos5422, there are two power line as following:
+	VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
+	        |--- DREX 1
+
+	VDD_INT |--- NoC_Core (parent device)
+		|--- G2D
+		|--- G3D
+		|--- DISP1
+		|--- NoC_WCORE
+		|--- GSCL
+		|--- MSCL
+		|--- ISP
+		|--- MFC
+		|--- GEN
+		|--- PERIS
+		|--- PERIC
+		|--- FSYS
+		|--- FSYS2
+
 Example1:
 	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 	power line (regulator). The MIF (Memory Interface) AXI bus is used to
-- 
1.9.1