linux-kernel - Re: [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table

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Message-ID: <20160415130549.GB8021@leverpostej>
Date:	Fri, 15 Apr 2016 14:05:49 +0100
From:	Mark Rutland <mark.rutland@....com>
To:	Masahiro Yamada <yamada.masahiro@...ionext.com>
Cc:	arm@...nel.org, devicetree@...r.kernel.org,
	Kumar Gala <galak@...eaurora.org>,
	linux-kernel@...r.kernel.org,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Will Deacon <will.deacon@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/2] arm64: dts: uniphier: change release address of
 spin-table

On Fri, Apr 15, 2016 at 07:30:47PM +0900, Masahiro Yamada wrote:
> The 8-byte register located at 0x59801200 on this SoC is dedicated
> for waking up secondary CPUs.  We can use it and save normal memory.

Generally, it is not safe to use MMIO registers to back spin-table. The
kernel maps the spin table location with cacheable attributes, so there
may be speculative accesses to any registes in the same (64K) page, and
a writeback may be larger than the 8-byte register width (which the
device might not accept, triggering an SError).

Given that, I do not think this is a good idea.

Thanks,
Mark.

> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@...ionext.com>
> ---
> 
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
> index 651c9d9..f73b09e 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
> @@ -77,7 +77,7 @@
>  			compatible = "arm,cortex-a72", "arm,armv8";
>  			reg = <0 0x000>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -85,7 +85,7 @@
>  			compatible = "arm,cortex-a72", "arm,armv8";
>  			reg = <0 0x001>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  
>  		cpu2: cpu@100 {
> @@ -93,7 +93,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0 0x100>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  
>  		cpu3: cpu@101 {
> @@ -101,7 +101,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0 0x101>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  	};
>  
> -- 
> 1.9.1
>