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Message-ID: <20160415222911.GR14441@codeaurora.org>
Date: Fri, 15 Apr 2016 15:29:11 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc: Mike Turquette <mturquette@...libre.com>,
David Airlie <airlied@...ux.ie>,
Thierry Reding <thierry.reding@...il.com>,
Rob Herring <robh+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Daniel Vetter <daniel@...ll.ch>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org, linux-sunxi@...glegroups.com,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Hans de Goede <hdegoede@...hat.com>,
Alexander Kaplan <alex@...tthing.co>,
Boris Brezillon <boris.brezillon@...e-electrons.com>,
Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
Rob Clark <robdclark@...il.com>
Subject: Re: [PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates
compatible
On 03/23, Maxime Ripard wrote:
> The Allwinner SoCs have a gate controller to gate the access to the DRAM
> clock to the some devices that need to access the DRAM directly (mostly
> display / image related IPs).
>
> Use a simple gates driver to support the one found in the A13 / R8 SoCs.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> Acked-by: Chen-Yu Tsai <wens@...e.org>
> Acked-by: Rob Herring <robh@...nel.org>
> ---
Acked-by: Stephen Boyd <sboyd@...eaurora.org>
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