Message-Id: <1460832906-24064-1-git-send-email-vishnupatekar0510@gmail.com>
Date:	Sun, 17 Apr 2016 02:55:04 +0800
From:	Vishnu Patekar <vishnupatekar0510@...il.com>
To:	maxime.ripard@...e-electrons.com, emilio@...pez.com.ar,
	wens@...e.org
Cc:	sboyd@...eaurora.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com
Subject: [PATCH 0/2] sunxi factors clock predivider handling

For allwinner A31 ahb1 and a83t ahb1 clocks have predivider for certain parent.

Currently, it's being handled in clock specific functions. 

A83t ahb1 and a31 ahb1 are similar clocks except a83t parent index 0b10 and 0b11
are pll6/prediv and a31 ahb1 parent index 0x11 is pll6/prediv.
with only this change, code duplication was needed.

To handle this, this patch adds predivider table with parent index, prediv 
shift and width, parents with predivider will have nonzero width.

Rate adjustment is moved from clock specific recalc function to generic factors
recalc. clock specific recalc was currently used only by a31 ahb1.

For getter, it differentiates parents with prediv, with non-zero prediv width.

I've tested this patch on a83t bpi-m3 board. I do not have a31 device.
a83t changes are not included in this patch, It'll be included in separate patch.

Vishnu Patekar (2):
  clk: sunxi: add predivider handling for factors clock
  clk: sunxi: add prediv table for a31 ahb1 clock

 drivers/clk/sunxi/clk-factors.c | 31 +++++++++++++++----------------
 drivers/clk/sunxi/clk-factors.h | 10 +++++++++-
 drivers/clk/sunxi/clk-sunxi.c   | 31 +++++++++----------------------
 3 files changed, 33 insertions(+), 39 deletions(-)

-- 
1.9.1

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