linux-kernel - Re: [PATCH] arm64: dts: uniphier: add /memreserve/ for spin-table release address

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Message-ID: <CAK7LNATtWyZtVWrW3nOYjN=aRvCO1w8Rvr6_JWm3QfMMPhrSAQ@mail.gmail.com>
Date:	Mon, 18 Apr 2016 17:55:14 +0900
From:	Masahiro Yamada <yamada.masahiro@...ionext.com>
To:	Mark Rutland <mark.rutland@....com>
Cc:	arm@...nel.org, devicetree@...r.kernel.org,
	Kumar Gala <galak@...eaurora.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Will Deacon <will.deacon@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] arm64: dts: uniphier: add /memreserve/ for spin-table
 release address

Hi Mark,


2016-04-18 17:45 GMT+09:00 Mark Rutland <mark.rutland@....com>:
> On Sat, Apr 16, 2016 at 02:58:58AM +0900, Masahiro Yamada wrote:
>> As Documentation/arm64/booting.txt says, the cpu-release-addr
>> location should be reserved.
>>
>> Signed-off-by: Masahiro Yamada <yamada.masahiro@...ionext.com>
>> ---
>>
>>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
>> index 651c9d9..90909d2 100644
>> --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
>> +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
>> @@ -42,6 +42,8 @@
>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>   */
>>
>> +/memreserve/ 0x80000100 0x00000008;
>> +
>
> Please add a comment above the memreserve to mention what it is
> protecting. That helps to avoid having this cargo-culted to cases where
> it is not needed.

OK, will do.


> I take it that the code for the spin-table is not in RAM, and does not
> need to be protected similarly?


I use U-Boot to boot Linux for this board.

The code for the spin-table is on SDRAM, and not protected.

I already recognize this problem.

The difficulty for U-Boot is that
U-Boot relocates itself to the top of the DRAM.
So, it is difficult to predict
where the code will be placed.

I will discuss this issue in the U-Boot ML.


So, My current solution is
pre-fetch the code for the spin-table onto I-cache.



-- 
Best Regards
Masahiro Yamada