linux-kernel - Re: [PATCH v2 07/13] MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic)

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Message-ID: <CAOLZvyGWBuUoo3C5V3L9g6Lbswf1cj6=6TSdgehuGeJch8-V=Q@mail.gmail.com>
Date:	Mon, 18 Apr 2016 16:34:10 +0200
From:	Manuel Lauss <manuel.lauss@...il.com>
To:	Paul Burton <paul.burton@...tec.com>
Cc:	Linux-MIPS <linux-mips@...ux-mips.org>,
	Ralf Baechle <ralf@...ux-mips.org>,
	James Hogan <james.hogan@...tec.com>,
	"# v4 . 1+" <stable@...r.kernel.org>,
	David Daney <david.daney@...ium.com>,
	Huacai Chen <chenhc@...ote.com>,
	"Maciej W. Rozycki" <macro@...ux-mips.org>,
	Paul Gortmaker <paul.gortmaker@...driver.com>,
	"Aneesh Kumar K.V" <aneesh.kumar@...ux.vnet.ibm.com>,
	LKML <linux-kernel@...r.kernel.org>,
	"Peter Zijlstra (Intel)" <peterz@...radead.org>,
	David Hildenbrand <dahi@...ux.vnet.ibm.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Jerome Marchand <jmarchan@...hat.com>,
	Markos Chandras <markos.chandras@...tec.com>,
	Alex Smith <alex.smith@...tec.com>,
	"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
Subject: Re: [PATCH v2 07/13] MIPS: mm: Fix MIPS32 36b physical addressing
 (alchemy, netlogic)

On Mon, Apr 18, 2016 at 11:35 AM, Paul Burton <paul.burton@...tec.com> wrote:
> There are 2 distinct cases in which a kernel for a MIPS32 CPU
> (CONFIG_CPU_MIPS32=y) may use 64 bit physical addresses
> (CONFIG_PHYS_ADDR_T_64BIT=y):
>
>   - 36 bit physical addressing as used by RMI Alchemy & Netlogic XLP/XLR
>     CPUs.
>
>   - MIPS32r5 eXtended Physical Addressing (XPA).

This hunk here gives me a build failure on Alchemy:

/home/mano/dev/db1200/kernel/linux/arch/mips/mm/init.c: In function
'__kmap_pgprot':
/home/mano/dev/db1200/kernel/linux/arch/mips/mm/init.c:116:28: error:
'_PFNX_MASK' undeclared (first use in this function)
   entrylo = (pte.pte_low & _PFNX_MASK);


> diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
> index 5bc663d..58e8bf8 100644
> --- a/arch/mips/include/asm/pgtable-bits.h
> +++ b/arch/mips/include/asm/pgtable-bits.h
> @@ -32,11 +32,11 @@
>   * unpredictable things.  The code (when it is written) to deal with
>   * this problem will be in the update_mmu_cache() code for the r4k.
>   */
> -#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
> +#if defined(CONFIG_XPA)
>
>  /*
> - * Page table bit offsets used for 64 bit physical addressing on MIPS32,
> - * for example with Alchemy, Netlogic XLP/XLR or XPA.
> + * Page table bit offsets used for 64 bit physical addressing on
> + * MIPS32r5 with XPA.
>   */
>  enum pgtable_bits {
>         /* Used by TLB hardware (placed in EntryLo*) */
> @@ -59,6 +59,27 @@ enum pgtable_bits {
>   */
>  #define _PFNX_MASK             0xffffff
>
> +#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
> +
> +/*
> + * Page table bit offsets used for 36 bit physical addressing on MIPS32,
> + * for example with Alchemy or Netlogic XLP/XLR.
> + */
> +enum pgtable_bits {
> +       /* Used by TLB hardware (placed in EntryLo*) */
> +       _PAGE_GLOBAL_SHIFT,
> +       _PAGE_VALID_SHIFT,
> +       _PAGE_DIRTY_SHIFT,
> +       _CACHE_SHIFT,
> +
> +       /* Used only by software (masked out before writing EntryLo*) */
> +       _PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3,
> +       _PAGE_NO_READ_SHIFT,
> +       _PAGE_WRITE_SHIFT,
> +       _PAGE_ACCESSED_SHIFT,
> +       _PAGE_MODIFIED_SHIFT,
> +};
> +

forgot _PFNX_MASK here?


Manuel