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Message-ID: <20160419090654.GN3217@sirena.org.uk>
Date: Tue, 19 Apr 2016 10:06:54 +0100
From: Mark Brown <broonie@...nel.org>
To: Jonathan Cameron <jic23@...nel.org>
Cc: Crestez Dan Leonard <leonard.crestez@...el.com>,
Peter Meerwald-Stadler <pmeerw@...erw.net>,
linux-iio@...r.kernel.org, linux-kernel@...r.kernel.org,
Hartmut Knaack <knaack.h@....de>,
Lars-Peter Clausen <lars@...afoo.de>,
Daniel Baluta <daniel.baluta@...el.com>
Subject: Re: [PATCH 1/5] max44000: Initial commit
On Mon, Apr 18, 2016 at 08:36:19PM +0100, Jonathan Cameron wrote:
> On 18/04/16 13:34, Mark Brown wrote:
> > Yes. I have to say that you are the first person I've encountered who
> > has been confused by this, I'm not sure why you'd expect writes to be
> > discarded.
> It confused me too :) To my mind a classic cache optimization would be
> to not write to the hardware if the value is already known to be as
> desired.
> Still, I guess it would add another check to identify which
> registers you really wanted to hammer whatever vs which can be assumed
> not to read the write is not worth the effort for this case that
> inherently won't be hit that often.
We'd also have to add another API for cases where someone explicitly
wants to write the same thing to the hardware, you get things like
latched "do it" bits in registers.
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