linux-kernel - Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock

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Message-ID: <20160419091823.GX4005@lukather>
Date:	Tue, 19 Apr 2016 11:18:23 +0200
From:	Maxime Ripard <maxime.ripard@...e-electrons.com>
To:	Stephen Boyd <sboyd@...eaurora.org>
Cc:	Mike Turquette <mturquette@...libre.com>,
	David Airlie <airlied@...ux.ie>,
	Thierry Reding <thierry.reding@...il.com>,
	Rob Herring <robh+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
	Daniel Vetter <daniel@...ll.ch>, devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	dri-devel@...ts.freedesktop.org, linux-sunxi@...glegroups.com,
	Laurent Pinchart <laurent.pinchart@...asonboard.com>,
	Hans de Goede <hdegoede@...hat.com>,
	Alexander Kaplan <alex@...tthing.co>,
	Boris Brezillon <boris.brezillon@...e-electrons.com>,
	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
	Rob Clark <robdclark@...il.com>
Subject: Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock

On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote:
> On 03/23, Maxime Ripard wrote:
> > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> > PLL7, clocked from a 3MHz oscillator, that drives the display related
> > clocks (GPU, display engine, TCON, etc.)
> > 
> > Add a driver for it.
> > 
> > Acked-by: Rob Herring <robh@...nel.org>
> > Acked-by: Chen-Yu Tsai <wens@...e.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> > ---
> 
> Acked-by: Stephen Boyd <sboyd@...eaurora.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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