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Message-ID: <CADRPPNRU=qy34p4hzYvzBPrt2uabSQfc0Xdd8K5v5B_JW01QJA@mail.gmail.com>
Date: Fri, 22 Apr 2016 00:33:22 -0500
From: Leo Li <pku.leo@...il.com>
To: Marc Zyngier <marc.zyngier@....com>
Cc: Minghuan Lian <Minghuan.Lian@....com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
lkml <linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Roy Zang <roy.zang@....com>, Mingkai Hu <mingkai.hu@....com>,
Stuart Yoder <stuart.yoder@....com>,
Yang-Leo Li <leoyang.li@....com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <Mark.Rutland@....com>
Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support
On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier <marc.zyngier@....com> wrote:
> On Mon, 7 Mar 2016 11:36:22 +0800
> Minghuan Lian <Minghuan.Lian@....com> wrote:
>
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@....com>
>
> Acked-by: Marc Zyngier <marc.zyngier@....com>
>
> The DT binding still needs an Ack from the DT maintainers though (cc'd).
Marc,
Who will be responsible to pick this driver? I see you are also one
of the maintainers for irqchip. Can you pick up the driver? The
binding has already gotten ACKed by the device tree maintainer.
Regards,
Leo
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