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Message-Id: <1461605698-12385-2-git-send-email-jarkko.sakkinen@linux.intel.com>
Date: Mon, 25 Apr 2016 20:34:08 +0300
From: Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
To: gregkh@...uxfoundation.org
Cc: Kai Huang <kai.huang@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>,
x86@...nel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)),
Borislav Petkov <bp@...e.de>,
Andy Lutomirski <luto@...nel.org>,
Boris Ostrovsky <boris.ostrovsky@...cle.com>,
Huang Rui <ray.huang@....com>,
Mathias Krause <minipli@...glemail.com>,
Wan Zongshun <Vincent.Wan@....com>,
linux-kernel@...r.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND
64-BIT))
Subject: [PATCH 1/6] x86: add SGX definition to cpufeature
From: Kai Huang <kai.huang@...ux.intel.com>
Signed-off-by: Kai Huang <kai.huang@...ux.intel.com>
---
arch/x86/include/asm/cpufeature.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 7ad8c94..f6be49f 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -208,6 +208,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
+#define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */
#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
--
2.7.4
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