linux-kernel - [PATCH locking 3/4] documentation: ACQUIRE applies to loads, RELEASE applies to stores

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Message-Id: <1461691328-5429-3-git-send-email-paulmck@linux.vnet.ibm.com>
Date:	Tue, 26 Apr 2016 10:22:07 -0700
From:	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To:	linux-kernel@...r.kernel.org
Cc:	mingo@...nel.org, corbet@....net, peterz@...radead.org,
	linux-doc@...r.kernel.org, dhowells@...hat.com,
	will.deacon@....com, dave@...olabs.net,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
Subject: [PATCH locking 3/4] documentation: ACQUIRE applies to loads, RELEASE applies to stores

From: Will Deacon <will.deacon@....com>

For compound atomics performing both a load and a store operation, make
it clear that _acquire and _release variants refer only to the load and
store portions of compound atomic. For example, xchg_acquire is an xchg
operation where the load takes on ACQUIRE semantics.

Cc: Paul E. McKenney <paulmck@...ux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Signed-off-by: Will Deacon <will.deacon@....com>
Acked-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Signed-off-by: Paul E. McKenney <paulmck@...ux.vnet.ibm.com>
---
 Documentation/memory-barriers.txt | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 8b11e54238bf..147ae8ec836f 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -498,6 +498,11 @@ And a couple of implicit varieties:
      This means that ACQUIRE acts as a minimal "acquire" operation and
      RELEASE acts as a minimal "release" operation.
 
+A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
+and RELEASE variants in addition to fully-ordered and relaxed (no barrier
+semantics) definitions.  For compound atomics performing both a load and a
+store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
+only to the store portion of the operation.
 
 Memory barriers are only required where there's a possibility of interaction
 between two CPUs or between a CPU and a device.  If it can be guaranteed that
-- 
2.5.2