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Message-ID: <5720C4F4.3050700@marvell.com>
Date:	Wed, 27 Apr 2016 15:56:04 +0200
From:	Lino Sanfilippo <lsanfil@...vell.com>
To:	Elad Kanfi <eladkan@...lanox.com>, <davem@...emloft.net>
CC:	<noamca@...lanox.com>, <linux-kernel@...r.kernel.org>,
	<abrodkin@...opsys.com>, <talz@...lanox.com>,
	<netdev@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] net: nps_enet: Sync access to packet sent flag

Hi,

On 27.04.2016 15:18, Elad Kanfi wrote:
> From: Elad Kanfi <eladkan@...lanox.com>
>
> Below is a description of a possible problematic
> sequence. CPU-A is sending a frame and CPU-B handles
> the interrupt that indicates the frame was sent. CPU-B
> reads an invalid value of tx_packet_sent.
>
> 	CPU-A				CPU-B
> 	-----				-----
> 	nps_enet_send_frame
> 	.
> 	.
> 	tx_packet_sent = true
> 	order HW to start tx
> 	.
> 	.
> 	HW complete tx
> 			    ------> 	get tx complete interrupt
> 					.
> 					.
> 					if(tx_packet_sent == true)
>
> 	end memory transaction
> 	(tx_packet_sent actually
> 	 written)
>
> Problem solution:
>
> Add a memory barrier after setting tx_packet_sent,
> in order to make sure that it is written before
> the packet is sent.

Should not those SMP memory barriers be paired? AFAIK you do not only have to make sure
that the value written by CPU-A actually is written to memory but also that CPU-B
reads that value from memory. At least this is what I have understood from memory-barriers.txt...

Regards,
Lino

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