lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Tue, 3 May 2016 08:40:47 +0100
From:	Marc Zyngier <marc.zyngier@....com>
To:	Robert Richter <rrichter@...iumnetworks.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>
Cc:	Will Deacon <will.deacon@....com>,
	Tomasz Nowicki <tn@...ihalf.com>,
	David Daney <david.daney@...iumnetworks.com>,
	Ashok Kumar <ashoks@...adcom.com>,
	Robert Richter <rrichter@...ium.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] irqchip, gicv3-its, numa: Enable Cavium ThunderX #23144
 workaround for ACPI

Hi Robert,

On 02/05/16 17:38, Robert Richter wrote:
> From: Robert Richter <rrichter@...ium.com>
> 
> In case of acpi the firmware does not provide node ids for cpus and
> its devices. Determine it from system topology special to Cavium
> ThunderX systems. This enables #23144 workaround for ACPI.
> 
> Signed-off-by: Robert Richter <rrichter@...ium.com>
> ---
>  drivers/irqchip/irq-gic-v3-its.c | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 494395274cf7..6eac0f3c1e56 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1107,11 +1107,13 @@ static void its_cpu_init_collection(void)
>  
>  		/* avoid cross node collections and its mapping */
>  		if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
> -			struct device_node *cpu_node;
> -
> -			cpu_node = of_get_cpu_node(cpu, NULL);
> +			int nid = of_node_to_nid(of_get_cpu_node(cpu, NULL));
> +			if (nid == NUMA_NO_NODE) {
> +				pr_warn_once("ITS: Updating cpu numa node ids\n");

I don't really understand the meaning of that message. What are you
updating here?

> +				nid = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 2);
> +			}
>  			if (its->numa_node != NUMA_NO_NODE &&
> -				its->numa_node != of_node_to_nid(cpu_node))

So you're going from something that was relatively generic
(of_node_to_nid) to something that is now completely hardcoding the
Cavium view of CPU topology. Doesn't ACPI have similar abstractions?

> +				its->numa_node != nid)
>  				continue;
>  		}
>  
> @@ -1443,6 +1445,15 @@ static void __maybe_unused its_enable_quirk_cavium_23144(void *data)
>  {
>  	struct its_node *its = data;
>  
> +	if (!IS_ENABLED(CONFIG_NUMA))
> +		return;
> +
> +	if (its->numa_node == NUMA_NO_NODE) {
> +		/* make ACPI work */
> +		its->numa_node = (its->phys_base >> 44) & 0x3;

How is that ACPI specific?

> +		pr_warn_once("ITS: Updating ITS numa node ids\n");
> +	}
> +
>  	its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
>  }
>  
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ