linux-kernel - [PATCH v3] Workaround for Broadcom NS2 gicv2m implementation

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Date:	Thu,  5 May 2016 09:32:00 -0700
From:	Ray Jui <ray.jui@...adcom.com>
To:	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Marc Zyngier <marc.zyngier@....com>
Cc:	linux-kernel@...r.kernel.org,
	bcm-kernel-feedback-list@...adcom.com,
	linux-arm-kernel@...ts.infradead.org,
	Ray Jui <ray.jui@...adcom.com>,
	Alex Barba <alex.barba@...adcom.com>
Subject: [PATCH v3] Workaround for Broadcom NS2 gicv2m implementation

Alex Barba <alex.barba@...adcom.com> discovered Broadcom NS2 GICv2m
implementation has an erratum where the MSI data needs to be the SPI number
subtracted by an offset of 32, for the correct MSI interrupt to be triggered.

We are now implementating the workaround based on readings from the MSI_IIDR
register.

Patch series is developed based on Linux v4.6-rc1 and available at:
https://github.com/Broadcom/arm64-linux/tree/gicv2m-iproc-v3

Changes from v2:
 - Improved the logic of dealing with MSI_IIDR readings by using a switch
statement suggested by Marc Zyngier

Changes from v1:
 - Changed from DT based approach to the approch similar to APM that is based
on readings from the MSI_IIDR register

Ray Jui (1):
  irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum

 drivers/irqchip/irq-gic-v2m.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

-- 
2.1.4