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Message-ID: <20160506182020.GC3492@codeaurora.org>
Date:	Fri, 6 May 2016 11:20:20 -0700
From:	Stephen Boyd <sboyd@...eaurora.org>
To:	Jiancheng Xue <xuejiancheng@...ilicon.com>
Cc:	mturquette@...libre.com, p.zabel@...gutronix.de,
	linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
	robh+dt@...nel.org, yanhaifeng@...ilicon.com,
	yanghongwei@...ilicon.com, suwenping@...ilicon.com,
	raojun@...ilicon.com, ml.yang@...ilicon.com, gaofei@...ilicon.com,
	zhangzhenxing@...ilicon.com, hermit.wangheming@...ilicon.com,
	jiangheng@...ilicon.com
Subject: Re: [PATCH 1/3] reset: hisilicon: add reset controller driver for
 hisilicon SOCs

On 04/23, Jiancheng Xue wrote:
> In most of hisilicon SOCs, reset controller and clock provider are
> combined together as a block named CRG (Clock and Reset Generator).
> This patch mainly implements the reset function.
> 
> Signed-off-by: Jiancheng Xue <xuejiancheng@...ilicon.com>
> Acked-by: Philipp Zabel <p.zabel@...gutronix.de>
> ---

Applied to clk-hi3519

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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