lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20160509071954.316726773@linuxfoundation.org>
Date:	Mon,  9 May 2016 09:21:33 +0200
From:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:	linux-kernel@...r.kernel.org
Cc:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	stable@...r.kernel.org, Sascha Hauer <s.hauer@...gutronix.de>,
	Steffen Trumtrar <s.trumtrar@...gutronix.de>,
	Ard Biesheuvel <ard.biesheuvel@...aro.org>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>,
	Kevin Hilman <khilman@...libre.com>
Subject: [PATCH 4.5 44/88] ARM: SoCFPGA: Fix secondary CPU startup in thumb2 kernel

4.5-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Sascha Hauer <s.hauer@...gutronix.de>

commit 5616f36713ea77f57ae908bf2fef641364403c9f upstream.

The secondary CPU starts up in ARM mode. When the kernel is compiled in
thumb2 mode we have to explicitly compile the secondary startup
trampoline in ARM mode, otherwise the CPU will go to Nirvana.

Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
Reported-by: Steffen Trumtrar <s.trumtrar@...gutronix.de>
Suggested-by: Ard Biesheuvel <ard.biesheuvel@...aro.org>
Signed-off-by: Dinh Nguyen <dinguyen@...nsource.altera.com>
Signed-off-by: Kevin Hilman <khilman@...libre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 arch/arm/mach-socfpga/headsmp.S |    1 +
 1 file changed, 1 insertion(+)

--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -13,6 +13,7 @@
 #include <asm/assembler.h>
 
 	.arch	armv7-a
+	.arm
 
 ENTRY(secondary_trampoline)
 	/* CPU1 will always fetch from 0x0 when it is brought out of reset.


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ