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Date: Thu, 12 May 2016 03:29:06 -0700 From: tip-bot for Yazen Ghannam <tipbot@...or.com> To: linux-tip-commits@...r.kernel.org Cc: tglx@...utronix.de, tony.luck@...el.com, bp@...en8.de, torvalds@...ux-foundation.org, bp@...e.de, aravindksg.lkml@...il.com, peterz@...radead.org, hpa@...or.com, luto@...capital.net, brgerst@...il.com, linux-kernel@...r.kernel.org, linux-edac@...r.kernel.org, dvlasenk@...hat.com, Yazen.Ghannam@....com, mingo@...nel.org Subject: [tip:ras/core] x86/RAS: Add SMCA support to AMD Error Injector Commit-ID: 754a92305980b1fecffe033dd3fdc49c37f8e4b0 Gitweb: http://git.kernel.org/tip/754a92305980b1fecffe033dd3fdc49c37f8e4b0 Author: Yazen Ghannam <Yazen.Ghannam@....com> AuthorDate: Wed, 11 May 2016 14:58:29 +0200 Committer: Ingo Molnar <mingo@...nel.org> CommitDate: Thu, 12 May 2016 09:08:23 +0200 x86/RAS: Add SMCA support to AMD Error Injector Use SMCA MSRs when writing to MCA_{STATUS,ADDR,MISC} and MCA_DE{STAT,ADDR} when injecting Deferred Errors on SMCA platforms. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@....com> Signed-off-by: Borislav Petkov <bp@...e.de> Cc: Andy Lutomirski <luto@...capital.net> Cc: Aravind Gopalakrishnan <aravindksg.lkml@...il.com> Cc: Borislav Petkov <bp@...en8.de> Cc: Brian Gerst <brgerst@...il.com> Cc: Denys Vlasenko <dvlasenk@...hat.com> Cc: H. Peter Anvin <hpa@...or.com> Cc: Linus Torvalds <torvalds@...ux-foundation.org> Cc: Peter Zijlstra <peterz@...radead.org> Cc: Thomas Gleixner <tglx@...utronix.de> Cc: Tony Luck <tony.luck@...el.com> Cc: linux-edac <linux-edac@...r.kernel.org> Link: http://lkml.kernel.org/r/1462971509-3856-8-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@...nel.org> --- arch/x86/ras/mce_amd_inj.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/x86/ras/mce_amd_inj.c b/arch/x86/ras/mce_amd_inj.c index 9e02dca..e69f470 100644 --- a/arch/x86/ras/mce_amd_inj.c +++ b/arch/x86/ras/mce_amd_inj.c @@ -290,14 +290,33 @@ static void do_inject(void) wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS, (u32)mcg_status, (u32)(mcg_status >> 32)); - wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b), - (u32)i_mce.status, (u32)(i_mce.status >> 32)); + if (boot_cpu_has(X86_FEATURE_SMCA)) { + if (inj_type == DFR_INT_INJ) { + wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DESTAT(b), + (u32)i_mce.status, (u32)(i_mce.status >> 32)); + + wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DEADDR(b), + (u32)i_mce.addr, (u32)(i_mce.addr >> 32)); + } else { + wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_STATUS(b), + (u32)i_mce.status, (u32)(i_mce.status >> 32)); + + wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_ADDR(b), + (u32)i_mce.addr, (u32)(i_mce.addr >> 32)); + } + + wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(b), + (u32)i_mce.misc, (u32)(i_mce.misc >> 32)); + } else { + wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b), + (u32)i_mce.status, (u32)(i_mce.status >> 32)); - wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b), - (u32)i_mce.addr, (u32)(i_mce.addr >> 32)); + wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b), + (u32)i_mce.addr, (u32)(i_mce.addr >> 32)); - wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b), - (u32)i_mce.misc, (u32)(i_mce.misc >> 32)); + wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b), + (u32)i_mce.misc, (u32)(i_mce.misc >> 32)); + } toggle_hw_mce_inject(cpu, false);
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