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Message-Id: <B30D094A-1E5A-4777-8F2A-C3D53AF89044@martin.sperl.org>
Date: Thu, 12 May 2016 17:28:57 +0200
From: Martin Sperl <kernel@...tin.sperl.org>
To: Stefan Wahren <stefan.wahren@...e.com>
Cc: Eric Anholt <eric@...olt.net>, Lee Jones <lee@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Rob Herring <robh+dt@...nel.org>,
linux-rpi-kernel@...ts.infradead.org,
Stephen Warren <swarren@...dotorg.org>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Russell King <linux@....linux.org.uk>,
Mark Rutland <mark.rutland@....com>, devicetree@...r.kernel.org
Subject: Re: [PATCH 0/4] add minimal bcm2835-sdram driver
> On 12.05.2016, at 16:50, Stefan Wahren <stefan.wahren@...e.com> wrote:
>
> Hi Martin,
>
>> kernel@...tin.sperl.org hat am 12. Mai 2016 um 14:38 geschrieben:
>>
>>
>> From: Martin Sperl <kernel@...tin.sperl.org>
>>
>> As the sdram clock is a critical clock to the system
>> the minimal bcm2835-sdram driver claims (and enables)
>> this clock and also exposes the corresponding sdram
>> registers via debugfs.
>
> sounds like this driver should fix an clock handling issue. Unfortunately this
> isn't a solution in case the driver is disabled.
Unfortunately there is no way around this - the driver has
to be enabled so that the sdram clock or the parent pll,
which typically is plld_core, never gets disabled.
The only other option would be marking the clock as critical
for those legacy drivers.
See also the discussions around the clock register for the
sdram clock, where we have the “normal” clock and some
pll as well - even if the “normal” clock is disabled,
then clearing the sdram register (or the parent) freezes
the system.
>
> Does the GPU firmware handle the SDRAM controller or is it initialized by
> bootcode?
>
AFAIK it is enabled in bootcode.bin and - as of now - the firmware
updates refresh cycles when SOC temperatures change.
FW checks every 30 seconds unless there is a key set in config.txt,
which - supposedly - produces a slight impact every 30 seconds to
the system.
Martin
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