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Message-ID: <CAD=FV=UNVHrGeKj0N_1WQvL+PNBTrPTj1xmk-63F4hJhPuvkug@mail.gmail.com>
Date: Fri, 13 May 2016 09:38:16 -0700
From: Doug Anderson <dianders@...omium.org>
To: Shawn Lin <shawn.lin@...k-chips.com>
Cc: Brian Norris <briannorris@...omium.org>,
Heiko Stuebner <heiko@...ech.de>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Xing Zheng <zhengxing@...k-chips.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
linux-clk <linux-clk@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 2/2] clk: rockchip: fix the rk3399 sdmmc sample shift
Shawn,
On Fri, May 13, 2016 at 12:46 AM, Shawn Lin <shawn.lin@...k-chips.com> wrote:
>> This should be possible to verify in one of two ways. If the TRM has
>> a typo and things truly _do_ start at 0 instead of 1, then:
>>
>> 1. There will be roughly mirrors of valid ranges.
>> 2. Things won't match up if we change tuning to use 180 course offsets
>> and the rest fine offsets.
>>
>> It would be ideal if you could confirm with the chip guys, but if you
>
>
> I have checked it before Xing upstreamed the code, but as your question on
> the TRM, I check it with the chip guys again.
>
> So the answer is that drv/sample stuff should refer to Mobile Strorage
> Host Controller section, and it will fit the future Socs from now on.
OK, awesome. I also did more quick tests by forcing dw_mmc to give me
extra details about the tuning. These tests agree with you.
Please consider this patch abandoned. Note that the previous patch
(1/2) is still good as far as I know, so just this patch (2/2) should
be abandoned.
Thanks! :)
-Doug
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