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Date:	Sat, 14 May 2016 11:22:12 +0200
From:	Christian Lamparter <chunkeey@...glemail.com>
To:	Arnd Bergmann <arnd@...db.de>
Cc:	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Felipe Balbi <felipe.balbi@...ux.intel.com>,
	linux-mips@...ux-mips.org, johnyoun@...opsys.com,
	gregkh@...uxfoundation.org, linux-usb@...r.kernel.org,
	linux-kernel@...r.kernel.org, a.seppala@...il.com,
	linuxppc-dev@...ts.ozlabs.org,
	Douglas Anderson <dianders@...omium.org>,
	Gregory Herrero <gregory.herrero@...el.com>,
	Mian Yousaf Kaukab <yousaf.kaukab@...el.com>,
	Marek Szyprowski <m.szyprowski@...sung.com>
Subject: Re: [PATCH v4] usb: dwc2: fix regression on big-endian PowerPC/ARM systems

On Friday, May 13, 2016 03:52:27 PM Arnd Bergmann wrote:
> A patch that went into Linux-4.4 to fix big-endian mode on a Lantiq
> MIPS system unfortunately broke big-endian operation on PowerPC
> APM82181 as reported by Christian Lamparter, and likely other
> systems.
> 
> It actually introduced multiple issues:
> 
> - it broke big-endian ARM kernels: any machine that was working
>   correctly with a little-endian kernel is no longer using byteswaps
>   on big-endian kernels, which clearly breaks them.
> - On PowerPC the same thing must be true: if it was working before,
>   using big-endian kernels is now broken. Unlike ARM, 32-bit PowerPC
>   usually uses big-endian kernels, so they are likely all broken.
> - The barrier for dwc2_writel is on the wrong side of the __raw_writel(),
>   so the MMIO no longer synchronizes with DMA operations.
> - On architectures that require specific CPU instructions for MMIO
>   access, using the __raw_ variant may turn this into a pointer
>   dereference that does not have the same effect as the readl/writel.
> 
> This patch is a simple revert for all architectures other than MIPS,
> in the hope that we can more easily backport it to fix the regression
> on PowerPC and ARM systems without breaking the Lantiq system again.
> 
> We should follow this up with a more elaborate change to add runtime
> detection of endianness, to make sure it also works on all other
> combinations of architectures and implementations of the usb-dwc2
> device. That patch however will be fairly large and not appropriate
> for backports to stable kernels.
> 
> Felipe suggested a different approach, using an endianness switching
> register to always put the device into LE mode, but unfortunately
> the dwc2 hardware does not provide a generic way to do that. Also,
> I see no practical way of addressing the problem more generally by
> patching architecture specific code on MIPS.
> 
> Signed-off-by: Arnd Bergmann <arnd@...db.de>
> Fixes: 95c8bc360944 ("usb: dwc2: Use platform endianness when accessing registers")
Thanks Arnd,

Tested-by: Christian Lamparter <chunkeey@...glemail.com>

dwc2 4bff80000.usbotg: Specified GNPTXFDEP=1024 > 256
dwc2 4bff80000.usbotg: EPs: 3, shared fifos, 2042 entries in SPRAM
dwc2 4bff80000.usbotg: DWC OTG Controller
dwc2 4bff80000.usbotg: new USB bus registered, assigned bus number 1
dwc2 4bff80000.usbotg: irq 33, io mem 0x00000000
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected

Regards,
Christian

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