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Date: Tue, 17 May 2016 10:35:51 +0530
From: Purna Chandra Mandal <purna.mandal@...rochip.com>
To: <linux-kernel@...r.kernel.org>
CC: <linux-mips@...ux-mips.org>, Ralf Baechle <ralf@...ux-mips.org>,
Purna Chandra Mandal <purna.mandal@...rochip.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
<linux-clk@...r.kernel.org>
Subject: [PATCH 02/11] clk: microchip: Initialize SOSC clock rate for PIC32MZDA.
Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: Purna Chandra Mandal <purna.mandal@...rochip.com>
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-pic32mzda.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/microchip/clk-pic32mzda.c b/drivers/clk/microchip/clk-pic32mzda.c
index 020a29a..210694b 100644
--- a/drivers/clk/microchip/clk-pic32mzda.c
+++ b/drivers/clk/microchip/clk-pic32mzda.c
@@ -118,6 +118,7 @@ static const struct pic32_sec_osc_data sosc_clk = {
.status_reg = 0x1d0,
.enable_mask = BIT(1),
.status_mask = BIT(4),
+ .fixed_rate = 32768,
.init_data = {
.name = "sosc_clk",
.parent_names = NULL,
--
1.8.3.1
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